Many technologies, such as video signal processing, require massive data handling and processing in a short time interval. Real-time video signal processing requires that the operating processors receive and process the video signal or at extremely fast rates. In order to process data quickly, multiple processors are used, as described in U.S. patent application Ser. No. 421,497, filed Oct. 13, 1989, which is incorporated by reference herein.
In a parallel processing system, such as that disclosed in the above-referenced application, many memories will be accessed simultaneously. With dynamic memory cells, a sense amplifier is used to read from and write to the cells through a plurality of bit lines. The sense amplifiers include N channel and P channel flip flops. At some point during a sense operation, the voltage on the bit lines may be such that a low impedance path is formed through an N channel and a P channel transistor, resulting in a voltage spike. With many simultaneous sense operations being performed simultaneously, a large voltage spike may occur which could generate excessive noise within the circuit.
Further, an arithmetic logic unit (ALU) is often associated with the sense amplifier such that data may be read from the memory, modified by the ALU, and written back to the memory. It is important that the sense amplifier be activated precisely at the moment that the calculation is completed. If the sense amplifier is activated before the calculation is complete, erroneous information may be written back into the memory. On the other hand, if the sense amplifier is activated too late, the write cycle is extended, reducing the speed of the circuit.
Therefore, a need has arisen for a sense amplifier/memory configuration which provides high speed operation without the danger of voltage spikes. Further, a need has arisen for a sense amplifier/ALU circuit which provides precise timing of sense operations in relation to ALU calculations.